1. Field of the Invention
The disclosed subject matter relates generally to the fabrication of semiconductor devices and, more particularly, to forming interconnect features, such as vias or lines, with reduced sidewall tapering.
2. Description of the Related Art
In modern integrated circuits, minimum feature sizes, such as the channel length of field effect transistors, have reached the deep sub-micron range, thereby steadily increasing performance of these circuits in terms of speed and/or power consumption and/or diversity of circuit functions. As the size of the individual circuit elements is significantly reduced, thereby improving, for example, the switching speed of the transistor elements, the available floor space for interconnect lines electrically connecting the individual circuit elements is also decreased. Consequently, the dimensions of these interconnect lines and the spaces between the metal lines have to be reduced to compensate for a reduced amount of available floor space and for an increased number of circuit elements provided per unit area.
Conventional dual damascene interconnect techniques typically result in lines and vias with significant levels of sidewall tapering (i.e., inward tapering in a direction from top to bottom). For example, the sidewall angles may be less than 85 degrees instead of an idealized 90 degrees. This sidewall tapering requires increased spacing between adjacent vias to provide adequate electrical separation, thereby reducing density.
The present application is directed to various methods for forming vias so as to eliminate or reduce the effects of one or more of the problems identified above.